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KH231
Fast Settling, Wideband Buffer/Amplifier (Av = 1 to 5)
Features
s s s s s s
General Description
The KH231 Buffer/Amplifier is a wideband operational amplifier designed specifically for high-speed, lowgain applications. The KH231 is based on a current feedback op amp topology-a unique design that both eliminates the gain-bandwidth tradeoff and permits unprecedented high-speed performance. (See table below.) The KH231 Buffer/Amplifier is the ideal design alternative to low precision open-loop buffers and oscillationprone conventional op amps. The KH231 offers precise gains from 1.000 to -5.000 and linearity that is a true 0.1%-even for demanding 50 loads. Open-loop buffers, on the other hand, offer a nominal gain of 0.95 0.03 and a linearity of only 3% for typical loads. A buffer's settling time may look impressive but it is usually specified at unrealistically large load resistances or when the effects of thermal tail are not included; the KH231 Buffer/Amplifier settles to 0.05% in 15ns-while driving a 100 load. Offsets and drifts, usually a low priority in conventional high-speed op amp designs, were not ignored in the KH231; the input offset voltage is typically 1mV and input offset voltage drift is only 10V/C. The KH231 is stable and oscillation-free across the entire gain range and since it's internally compensated, the user is saved the trouble of designing external compensation networks and having to "tweak" them in production. The absence of a gain-bandwidth tradeoff in the KH231 allows performance to be predicted easily; the table below shows how the bandwidth is affected very little by changing the gain setting. The KH231 is constructed using thin film resistor/bipolar transistor technology, and is available in the following versions: The KH231 is constructed using thin film resistor/bipolar transistor technology, and available in these versions:
KH231AI KH231AK KH231AM
-2 -5 Units MHz ns V/ns ns
165MHz closed-loop - -3dB bandwidth 15ns settling to 0.05% 1mV input offset voltage, 10V/C drift 100mA output current Excellent AC and DC linearity Direct replacement for CLC231
Applications
s s s s
Driving flash A/D converters Precision line driving (a gain of 2 cancels matched-line losses) DAC current-to-voltage conversion Low-power, high-speed applications (50mW @ 5V)
Small Signal Pulse Response Output Voltage (400mV/div)
Av = 2
Av = -2
Time (5ns/div)
Bottom View
ICC Adjust Case ground GND 7 Adjust -VCC 8 9 -VCC V+ 6 10 Collector Supply Output Supply Voltage
Non-Inverting Input Inverting Input Not Connected
+
V- 5 NC 4 3 Case ground GND 2
4 4
-
11 Vo 12 +VCC
Collector Supply
1 Supply Voltage
Adjust +VCC ICC Adjust
Pins 2 and 8 are used to adjust the supply current or to adjust the offset voltage (see text). These pins are normally left unconnected.
-25C to +85C -55C to +125C -55C to +125C
Typical Performance
Gain Setting Parameter 1 2 5 -1 -3dB bandwidth 180 165 130 rise time (2V) 1.8 2.0 2.5 slew rate 2.5 3.0 3.0 settling time (to 0.1%) 12 12 12 165 150 115 2.0 2.2 2.9 3.0 3.0 3.0 12 12 15
KH231HXC KH231HXA
-55C to +125C -55C to +125C
12-pin TO-8 can 12-pin TO-8 can, features burn-in & hermetic testing 12-pin TO-8 can, environmentally screened and electrically tested to MIL-STD-883 SMD#: 5962-8959401HXC SMD#: 5962-8959401HXA
REV. 1A February 2001
DATA SHEET
KH231
KH231 Electrical Characteristics (TA = +25C, Av = +2V, VCC = 15V, RL = 100, Rf = 250; unless specified)
PARAMETERS Ambient Temperature Ambient Temperature FREQUENCY DOMAIN RESPONSE -3dB bandwidth (note 2) large-signal bandwidth gain flatness (note 2) peaking peaking rolloff group delay linear phase deviation reverse isolation non-inverting inverting TIME DOMAIN RESPONSE rise and fall time settling time to 0.05% to 0.1% overshoot slew rate (overdriven input) overload recovery <50ns pulse, 200% overdrive CONDITIONS KH231AI KH231AK/AM/HXC/HXA Vo 2Vpp Vo 10Vpp Vo 2Vpp 0.1 to 50MHz >50MHz at 100MHz to 100MHz to 100MHz TYP +25C +25C 165 95 0.1 0.1 0.4 3.5 0.5 0.5 53 36 2V step 10V step 5V step 2.5V step 5V step <1% error 120 -55 -59 -153 70 1 10 5.0 50 10 125 50 46 18 400 1.3 5, 37 12 - <-47 <-47 <-150 <100 <4.0 <25 <29 <125 <31 <200 >45 >40 <22 >100 <2.5 - >11 - <-47 <-47 <-150 <100 <2.0 <25 <21 <125 <15 <200 >45 >40 <22 >200 <2.5 - >11 - <-47 <-47 <-150 <100 <4.5 <25 <31 <125 < 35 <200 >45 >40 <22 >400 <2.5 - >11 ns dBc dBc dBm(1Hz) Vrms mV V/C A nA/C A nA/C dB dB mA k pF , nH V OR HD2 HD3 SNF INV VIO DVIO IBN DIBN IBI DIBI PSRR CMRR ICC RIN CIN RO VO 2.0 5.0 15 12 5 3.0 MIN & MAX RATINGS -25C -55C >145 >80 <0.6 <1.5 <0.6 - <2.0 >43 >26 <2.4 <7.0 - <22 <15 >2.5 +25C +25C >145 >80 <0.3 <0.3 <0.6 - <2.0 >43 >26 <2.3 <6.5 - <17 <10 >2.5 +85C +125C >120 >60 <0.6 <0.8 <1.0 - <2.0 >43 >26 <2.7 <6.5 - <22 <15 >1.8 MHz MHz dB dB dB ns dB dB ns ns ns ns % V/ns SSBW FPBW GFPL GFPH GFR GD LPD RINI RIIN TRS TRL TS TSP OS SR UNITS SYM
NOISE AND DISTORTION RESPONSE 2nd harmonic distortion 0dBm, 20MHz 3rd harmonic distortion 0dBm, 20MHz equivalent input noise noise floor >5MHz integrated noise 5MHz to 200MHz STATIC, DC PERFORMANCE * input offset voltage average temperature coefficient * input bias current average temperature coefficient * input bias current average temperature coefficient * power supply rejection ratio common mode rejection ratio * supply current MISCELLANEOUS PERFORMANCE non-inverting input resistance non-inverting input capacitance output impedance output voltage range
non-inverting inverting
no load DC @ 100MHz no load
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.
Absolute Maximum Ratings
VCC Io common mode input voltage, Vo differential input voltage thermal resistance junction temperature operating temperature storage temperature lead temperature (soldering 10s) note 1: * 20V 100mA (see Vcm and Vo limits plot on page 3) 3V (see thermal model) +175C AI: -25C to +85C AK/AM: -55C to +125C -65C to +150C +300C
Recommended Operating Conditions
VCC Io common mode input voltage gain range note 3: 5V to 15V 75mA (|VCC| -5)V 1 to 5
note 4:
note 2:
AI/AK/AM/HXC/HXA 100% tested at +25C AK/AM/HXC/HXA 100% tested at +25C and sample tested at -55C and +125C AI sample tested at +25C The output amplitude used in testing is 0.63Vpp. Performance is guaranteed for conditions listed.
In the noninverting configuration, care should be taken when choosing Ri, the input impedance setting resistor; bias currents of typically 5A but as high as 24A can create an input signal large enough to cause overload. It is therefore recommended that Ri < (VCC/Av)/24A. These ratings protect against damage to the input stage caused by saturation of either the input or output stages at lower supply voltages, and against exceeding transistor collector-emitter breakdown ratings at high supply voltages. Vout(max) is calculated by assuming no output saturation. Saturation is allowed to occur up to this calculated level of Vout. Vcm is defined as the voltage at the non-inverting input, pin 6.
REV. 1A February 2001
2
KH231
DATA SHEET
KH231 Typical Performance Characteristics (T
Non-Inverting Frequency Response Normalized Magnitude (1dB/div) Normalized Magnitude (1dB/div)
Gain Av = 2 Gain
A
= +25C, Av = +2, VCC = 15V, RL = 100, Rf = 250; unless specified)
Broadband Gain and Phase
Gain Av = 2
Inverting Frequency Response
Magnitude (10dB/div)
Av = -2
Phase (180 deg/div)
Phase (45 deg/div)
Phase (45 deg/div)
Av = 5 Av = 1 Phase Av = 5 Av = 2 Av = 1
Av = -5 Phase Av = -5 Av = -2 Av = -1 Av = -1
Phase
0
100
200
0
100
200
0
500
1000
Frequency (MHz) Bandwidth vs. VCC
1.2
Av = 2
Frequency (MHz) Frequency Response vs. RL
Frequency (MHz) Full Power Gain vs. Frequency
Av = 2 Vo = 10Vpp RL = 1K Inverting
Relative Bandwidth
1.0
(1dB/div)
(1dB/div)
Pins 1 and 2 Shorted Pins 8 and 9 shorted
RL = 200 RL = 50
Non-Inverting
0.8
0.6
RL = 100
0.4 4 6 8 10 12 14 16 0 125 250 0 100 200
VCC (V) 2nd and 3rd Harmonic Distortion Intercept
130 50
Frequency (MHz) 2-Tone, 3rd Order Intermod. Intercept
100
Av = 2
Frequency (MHz) Equivalent Input Noise
100
Inverting Current 23.8pA/Hz
Noise Voltage (nV/Hz)
Intercept Point (+dBm)
110 90 70 50 30 1k
2nd harmonic intercept exceeds +120dBm below 350KHz
I2
Intercept Point (+dBm)
45 40 35 30 25 20
Noise Current (pA/Hz)
10
Non-Inverting Current 2.5pA/Hz
10
3rd harmonic intercept exceeds +65dBm below 350KHz
I3
Voltage 2.8nV/Hz
1 0 20 40 60 80 100 100 1k 10k 100k 1M 10M
10k
100k
1M
10M
100M
1 100M
Frequency (Hz) Small Signal Pulse Response Output Voltage (400mV/div)
Frequency (MHz) Large Signal Pulse Response
0.20 0.15
Frequency (Hz) Settling Time
Output Voltage (2V/div)
Settling Error (%)
Av = 2
Av = 2
0.10 0.05 0 -0.05 -0.10 -0.15 -0.20
5ns/div
50ns/div
Av = -2
Av = -2
Time (5ns/div)
Time (5ns/div)
Time (ns)
CMRR and PSRR
20
PSRR
Vcm and Vo Voltage Limits
|Vout| max |Vcm| max
50
PSRR/CMRR (dB)
CMRR
40 30 20 10
Indicated Voltage
15
|Vout| max
10
note 4 on page 2
5
|Vcm| max
0 1 10 100 1k 10k 100k 1M 10M 100M 0 5 10 15 20
Frequency (Hz)
|VCC| (V)
REV. 1A February 2001
3
DATA SHEET
KH231
Operation The KH231 Buffer/Amplifier is based on the current feedback op amp topology, a design that uses current feedback instead of the usual voltage feedback. The use of the KH231 is basically the same as that of the conventional op amp (see Figures 1 and 2). Since the device is designed specifically for low gain applications, the best performance is obtained when the circuit is used at gains between 1 and 5. Additionally, performance is optimum when a 250 feedback resistor is used.
type pc boards and methods. Sockets with small, short pin receptacles may be used with minimal performance degradation although their use is not recommended. During pc board layout keep all traces short and direct The resistive body of Rg should be as close as possible to pin 5 to minimize capacitance at that point. For the same reason, remove ground plane from the vicinity of pins 5 and 6. In other areas, use as much ground plane as possible on one side of the board. It is especially important to provide a ground return path for current from the load resistor to the power supply bypass capacitors. Ceramic capacitors of 0.01 to 0.1f (with short leads) should be less than 0.15 inches from pins 1 and 9. Larger tantalum capacitors should be placed within one inch of these pins. VCC connections to pins 10 and 12 can be made directly from pins 9 and 1, but better supply rejection and settling time are obtained if they are separately bypassed as in figures 1 and 2. To prevent signal distortion caused by reflections from impedance mismatches, use terminated microstrip or coaxial cable when the signal must traverse more than a few inches. Since the pc board forms such an important part of the circuit, much time can be saved if prototype boards of any high frequency sections are built and tested early in the design phase. Evaluation boards designed for either inverting or non-inverting gains are available. Distortion and Noise The graphs of intercept point, I2 and I3, versus frequency on the preceding page make it easy to predict the distortion at any frequency given the output voltage of the KH231. First, convert the output voltage (Vo) to Vrms = (Vpp/22) and then to P = [(10log10(20Vrms2)] to get the power output in dBm. At the frequency of interest, its 2nd harmonic will be S2 = (I2-P)dB below the level of P. Its third harmonic will be S3 = 2(I3- P)dB below P, as will the two-tone third order intermodulation products. These approximations are useful for P < -1dB compression levels. Approximate noise figure can be determined for the KH231 using the equivalent input noise graph on the preceding page. The following equation can be used to determine noise figure (F) in dB.
2 inR f 2 2 Vn + Av2 F = 10log 1 + 4kTR s f
+15V 3.9
33 0.1
6 1 12 11 10 3,7 9
.01 Capactance in F
Vin Ri 49.9 Rg
+ -
KH231
5
Vo 250 RL 100
-15V 3.9
33 0.1 .01
A v = 1+
Rf Rg
Rf = 250
Figure 1: Recommended non-inverting gain circuit
+15V 3.9
33 0.1 100 Rg
6 1 12 11 10 3,7 9
.01 Capactance in F
+ -
KH231
5
Vo 250 RL 100
Vin Ri
-15V 3.9
33 0.1 .01
Rf Av = - Rg Rf = 250 For Zin = 50, select Rg || Ri = 50
Figure 2: Recommended inverting gain circuit Layout Considerations To assure optimum performance the user should follow good layout practices which minimize the unwanted coupling of signals between nodes. During initial breadboarding of the circuit use direct point to point wiring, keeping the lead lengths to less than 0.25". The use of solid, unbroken ground plane is helpful. Avoid wire-wrap 4

Where Vn is the rms noise voltage and in is the rms noise current. Beyond the breakpoint of the curves (i.e., where they are flat), broadband noise figure equals spot noise figure, so f should equal one (1) and Vn and in should be read directly off the graph. Below the breakpoint, the noise must be integrated and f set to the appropriate bandwidth.
REV. 1A February 2001
KH231
DATA SHEET
Offset Voltage Adjustment If trimming of the input offset voltage (Vos = Vni -Vin) is desired, a resistor value of 10k to 1M placed between pins 8 and 9 will cause Vos to become more negative by 8mV to 0.2mV respectively. Similarly, a resistor placed between pins 1 and 2 will cause Vos, to become more positive. Thermal Considerations At high ambient temperatures or large internal power dissipations, heat sinking is required to maintain acceptable junction temperatures. Use the thermal model on the previous page to determine junction temperatures. Many styles of heat sinks are available for TO-8 packages; the Thermalloy 2240 and 2268 are good examples. Some heat sinks are the radial fin type which cover the pc board and may interfere with external components. An excellent solution to this problem is to use surface mounted resistors and capacitors. They have a very low profile and actually improve high frequency performance. For use of these heat sinks with conventional components, a 0.1" high spacer can be inserted under the TO-8 package to allow sufficient clearance.
Tcase 100C/W Tj(pnp) Ppnp 100C/W Tj(npn) Pnpn 17.5C/W Tj(circuit) Pcircuit + Tambient ca
ca = 65C/W for the KH231 without heat sink in still air. 30C/W for the KH231 with a Wakefield 215 heat sink in still air. 10C/W for the KH231 with a Wakefield 215 heat sink at 300 ft/min air. 30C/W for the KH231 with a Thermalloy 2240A heat sink in still air. 5C/W for the KH231 with a Thermalloy 2240A heat sink at 500 ft/min air. For example, with the KH231 operating at 15V while driving a 100 load at 15Vpp output (50% duty cycle pulse waveform, DC = 0), P(npn) = P(pnp) = 190mW (Rcol = 33) and P(cir) = 0.48W. Then with the Wakefield 215 heat sink and air flow of 300 ft/min the output transistors' Tj is 28C above ambient and worst case Tj in the rest of the circuit is 32C above ambient. In still air, however, the rise in Tj is 45C and 49C, respectively. With no heat sink, the rise in Tj is 75C and 79C, respectively! Under most conditions, HEAT SINKING IS REQUIRED. Other methods of heat sinking may be used, but for best results, make contact with the base of the KH231 package, use a large thermal capacity heat sink and use forced air convection. Low VCC Operation: Supply Current Adjustment The KH231 is designed to operate on supplies as low as 5V. In order to improve full bandwidth at reduced supply voltages, the supply current (ICC) must be increased. The plot of Bandwidth vs. VCC, shows the effect of shorting pins 1 and 2 and pins 8 and 9; this will increase both bandwidth and supply current. Care should be taken to not exceed the maximum junction temperatures; for this reason this technique should not be used with supplies exceeding 10V. For intermediate values of VCC, external resistors between pins 1 and 2 and pins 8 and 9 can be used.
P(circuit) = (ICC)((+VCC) - (VCC)) where ICC = 16mA at 15V P(xxx) = [(VCC) - Vout - (Icol) (Rcol + 4)] (Icol) (%Duty) For positive Vo and VCC, this is the power in the npn device. For negative Vo and VCC, this is the power in the pnp device. Icol = Vo/RL or 4mA, whichever is greater. (Include feedback R in RL.) Rcol is a resistor (33 recommended) between the xxx collector and VCC. The limiting factor for output current and voltage is junction temperature. Of secondary importance is I(out), which should not exceed 150mA. Tj(pnp) = P(pnp) (100 + ca) + (P(cir) + P(npn))(ca) + Ta, similar for Tj(npn). Tj(cir) = P(cir)(48 + ca) + (P(pnp) + P(npn))(ca) + Ta.
REV. 1A February 2001
5
DATA SHEET
KH231
KH231 Package Dimensions
A L e1 e2
7 6 8 9 10 11 12
D
D1
e
5 4
b F
k
3 2 1
k1
TO-8
SYMBOL
A b D D1 e e1 e2 F k k1 L
INCHES
Minimun 0.142 0.016 0.595 0.543 Maximum 0.181 0.019 0.605 0.555
MILIMETERS
Minimum 3.61 0.41 15.11 13.79 Maximum 4.60 0.48 15.37 14.10
NOTES: Seal: cap weld Lead finish: gold per MIL-M-38510 Package composition: Package: metal Lid: Type A per MIL-M-38510
0.400 BSC 0.200 BSC 0.100 BSC 0.016 0.026 0.026 0.310 0.030 0.036 0.036 0.340
10.16 BSC 5.08 BSC 2.54 BSC 0.41 0.66 0.66 7.87 0.76 0.91 0.91 8.64
45 BSC
45 BSC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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(c) 2001 Fairchild Semiconductor Corporation

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